Delta-sigma modulation is a kind of analog-to-digital (ADC) or digital-to-analog (DAC) conversion derived from delta modulation. In general, the ADC or DAC circuits that are used to implement the delta-sigma modulation technique can be designed using relatively low-cost CMOS components. As a result, delta-sigma modulation has come into more widespread use as silicon technology has progressed. One principle of delta-sigma modulation is to make an evaluation of a signal, measure the error, integrate the error, and then compensate for the error. The mean output value is equal to the mean input value if the integral of the error is finite. The number of integrator, which corresponds to the number of feedback loops, indicates the order of the delta-sigma modulator.
To provide a high definition transfer of signals, delta-sigma modulators may use oversampling and/or noise shaping techniques. As shown in FIG. 1, oversampling may reduce quantization errors in-band using a high sampling frequency because the sum of the quantization error is constant within the sampling frequency. Noise shaping techniques push the quantization error out of the in-band. The amount of noise shaping applied is dependent on the delta-sigma modulator's order. By using both oversampling and noise shaping, the noise rate in the signal band may be reduced and the signal-to-noise ratio may be improved.
FIG. 2 illustrates a conventional delta-sigma modulator that comprises a loop filter 10, subtractor circuit 15, adder circuit 12, and an N-bit quantizer 20 that are connected as shown. The subtractor 15 computes the difference between the input signal Xin and the output from the quantizer 20. The difference is cumulated in the loop filter 10 and the cumulated difference is provided as an input to the quantizer 20. Unfortunately, the modulator of FIG. 2 includes a “dead zone,” which corresponds to some inputs that cannot be precisely quantized due to the loop filter's order and the characteristics of the quantizer 20. The conventional delta-sigma modulator may also be adversely affected by pattern noise or idle channel noise, i.e., a periodic spectrum that has a higher magnitude than the quantization error. To address such deficiencies, dither signals may be used as shown in FIG. 2 (DITHER1 11, DITHER2 13, and DITHER3 21) or more advanced loop filters may be used.
In an environment affected by pattern noise such as that shown in FIG. 3, a conventional delta-sigma modulator in response to static or direct current (DC) inputs attempts to equal on average the input level with repetitive patterns. A higher order modulator may decrease pattern noise, but typically cannot remove it completely. As discussed above, dithering may be included at the input to the quantizer. Dithering signals, however, are pseudo-random noise signals (non-periodic noise signals) that are themselves essentially a noise source. As shown in FIG. 2, if dither signals are added at the subtractor 15, the adder 12, and in the feedback path, then the magnitude of the input Xin is reduced by the added dither amount. Even though unwanted tone noise may be reduced by the dithering signals, the white noise may be increased and, because the magnitude of the input signal Xin is reduced, the signal-to-noise (SNR) ratio is reduced. Moreover, using a higher order modulator and/or dithering increases the complexity of the modulator circuit.
Another source of errors in delta-sigma modulators comes from the internal linearity error of a DAC as the resolution of the quantizer increases. Noise shaping cannot be used to address the internal linearity errors of the DAC so the error is output to an output terminal. To reduce the linearity error of a DAC, dynamic weight averaging (DWA) technology has been used.
FIG. 4 illustrates the conventional delta-sigma modulator of FIG. 2 that further includes a DWA capability. Referring to FIG. 4, the delta-sigma modulator includes a subtractor 15, loop filter 10, adder 12, N-bit quantizer 20, thermometer decoder 30, DWA decoder 40, and DAC that are connected as shown. Dither is added to the input of the quantizer 20 and the DAC is implemented as an analog low pass filter (LPF). The DWA decoder 40 shifts and outputs the output of the thermometer decoder 30. Differences in the number of zeros and ones input to the DWA decoder 40 determine the output of the DWA decoder 40. If the number of zeros and ones are the same, then the DAC 50 output is “0.” If, however, the number of ones exceeds the number of zeros, then the DAC 50 output is “1.”
The left bits of the thermometer decoder 30 are “1 (+err)”, “1,” “1,” “1,” and “1.” If the DWA decoder 40 is not used and the DAC 50 is subject to linearity errors, then the errors cumulate in the DAC 50 in a unidirectional fashion and may be viewed as tone noise. The left bits of the DWA decoder 40 are “0 (−err)”, “1 (+err),” “0,” “1,” and “1.” If the output of the thermometer decoder 30 is input to the DWA decoder 40, then the cumulated errors in the DAC 50 may be reduced. Adding a dither signal to the input of the quantizer has been used to address the problem of idle channel noise and tone noise in a multi-bit DAC. For example, FIG. 5 is a reproduction of FIG. 1A from U.S. Pat. No. 6,473,019 to Ruha et al. of a multi-bit sigma-delta modulator circuit in which a dither signal is added to the input of a quantizer. Unfortunately, in such configurations the magnitude of the input signal is typically reduced so that the maximum swing range is not exceeded when the dither signal is added to the input signal. As a result, white noise is increased and the SNR is reduced.